ASIC Chip Architecture: How Mining Chips Work

Introduction

At the heart of every Bitcoin miner sits a tiny silicon chip that does one thing extraordinarily well: compute SHA-256 hashes. These chips — called ASICs (Application-Specific Integrated Circuits) — are purpose-built for mining, and understanding their architecture is essential for anyone who repairs, operates, or builds mining hardware.

This article takes you inside the ASIC mining chip. We will explore why ASICs dominate mining, how the SHA-256 pipeline is implemented in silicon, what a die looks like under the microscope, how voltage and frequency interact to determine performance and efficiency, and how Bitmain's chip lineup has evolved over multiple generations. By the end, you will have the foundational knowledge to reason about chip behavior, diagnose failures, and understand the engineering tradeoffs that define modern mining hardware.

ASIC vs GPU vs CPU: Why ASICs Dominate Mining

To understand why ASICs exist, you need to understand the problem they solve. Bitcoin mining requires computing the SHA-256 hash function — twice — on a block header, billions of times per second, while incrementing a nonce value. The miner that finds a hash below the network's target difficulty wins the block reward.

The Compute Spectrum

Every computing device sits on a spectrum from general-purpose to fully specialized:

*Per-chip figures vary by generation. System-level J/TH for a modern S21 Pro is around 15 J/TH.

Why CPUs and GPUs Cannot Compete

A CPU is designed to handle any instruction thrown at it: branching, memory access, floating-point math, encryption, video decoding, and millions of other operations. This generality comes at a cost — the transistors dedicated to branch prediction, out-of-order execution, cache hierarchies, and instruction decoding are all wasted silicon when the only task is SHA-256.

A GPU improves on this by offering thousands of simpler cores running in parallel. GPUs were the dominant mining hardware from 2011 to 2013. However, each GPU core still carries overhead for general-purpose computation: register files, shared memory, texture units, and a flexible instruction set.

An ASIC strips away everything that is not SHA-256. Every transistor on the die serves exactly one purpose: hashing. There is no instruction decoder, no cache, no branch predictor. The result is a chip that computes SHA-256 at orders of magnitude better performance-per-watt than any general-purpose processor.

The Tradeoff

The disadvantage of an ASIC is obvious: it can only do one thing. If the Bitcoin network switched to a different hash algorithm tomorrow, every SHA-256 ASIC in the world would become paperweights. This rigidity is the price paid for extreme efficiency.

SHA-256 Hashing Pipeline Internals

To understand an ASIC mining chip, you need to understand what it computes. Bitcoin mining uses double SHA-256: the block header is hashed with SHA-256, and the result is hashed again. The miner varies the 32-bit nonce field in the header, checking whether each resulting hash meets the difficulty target.

SHA-256 in Brief

SHA-256 processes data in 512-bit (64-byte) blocks. For each block, it performs 64 rounds of computation, where each round involves:

1. Message schedule expansion — deriving 64 words from the 16-word input block
2. Compression function — updating eight 32-bit state variables (a through h) using bitwise operations, additions, and predefined constants

# Pseudocode for one SHA-256 round
T1 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]
T2 = Sigma0(a) + Maj(a, b, c)

h = g
g = f
f = e
e = d + T1
d = c
c = b
b = a
a = T1 + T2

The key operations are:

• Sigma0, Sigma1 — bitwise rotation and XOR combinations
• Ch (Choice) — (e AND f) XOR (NOT e AND g)
• Maj (Majority) — (a AND b) XOR (a AND c) XOR (b AND c)
• 32-bit modular addition — the most complex operation in the pipeline

How ASICs Implement This in Hardware

In an ASIC, each SHA-256 round is implemented as a fixed combinational logic circuit. There is no software, no instruction fetch, no program counter. The logic gates directly compute the Sigma, Choice, and Majority functions using hardwired connections between flip-flops and adders.

A single hashing core in an ASIC chip typically implements the full 64-round SHA-256 compression as a pipelined datapath:

The Double-Hash Optimization

Since Bitcoin requires SHA-256(SHA-256(header)), a mining ASIC must perform the hash twice. However, the 80-byte block header is split across two SHA-256 blocks:

• Block 1 (bytes 0-63): Contains version, previous block hash, and the first part of the Merkle root. This is constant for a given job and is computed once by the control board, then sent to the chip as a midstate.
• Block 2 (bytes 64-79 + padding): Contains the end of the Merkle root, timestamp, difficulty bits, and the nonce. Only this block changes per attempt.

Block Header (80 bytes):
[version | prev_hash | merkle_root_part1] ← SHA-256 Block 1 (midstate, precomputed)
[merkle_root_part2 | time | bits | nonce] ← SHA-256 Block 2 (varies per attempt)

Parallelism Through Cores

A single hashing core can produce one hash result per clock cycle (in a fully pipelined design). To achieve terahash-level performance, each chip contains hundreds to thousands of cores running in parallel. For example, the BM1366 is estimated to contain over 800 hashing cores, each independently working through its assigned nonce range.

Die Architecture: Cores, Compute Units, and I/O

An ASIC mining chip's die (the actual silicon) is organized into several distinct regions, each serving a specific purpose.

Core Array

The largest portion of the die — typically 70-85% of the silicon area — is devoted to the hashing core array. This is a grid of identical SHA-256 compute units tiled across the die. Each core is a self-contained pipeline that:

• Accepts a job (midstate + block tail)
• Iterates through its assigned nonce range
• Reports valid nonces back to the I/O controller

The cores are grouped into compute domains (sometimes called "groups" or "engines"). Each domain shares a local clock tree and may have independent nonce range assignments. This hierarchical organization simplifies clock distribution and reduces wire congestion.

PLL (Phase-Locked Loop)

Every mining ASIC contains one or more PLLs that generate the internal clock from an external reference (typically 25 MHz crystal). The PLL multiplies this reference frequency to produce the core clock — commonly 400 MHz to 800 MHz depending on the chip generation and operating conditions.

// Example: PLL register configuration for BM1366
// Setting core clock to 500 MHz from 25 MHz reference
// PLL output = (FBDIV / REFDIV) * REF_CLK / POSTDIV
// 500 MHz = (40 / 1) * 25 MHz / 2

#define BM1366_PLL_REFDIV    1
#define BM1366_PLL_FBDIV     40
#define BM1366_PLL_POSTDIV1  2
#define BM1366_PLL_POSTDIV2  1

The PLL is a critical block because the core clock directly determines hashrate. Higher frequency means more hashes per second — but also more power consumption and heat. See the Clock Distribution & PLL article for a deeper exploration.

Communication Interface

The I/O block handles all external communication. In Bitmain chips, this is a UART-based serial interface operating at baud rates typically between 1.5 Mbps and 6.25 Mbps (depending on chip generation and configuration). The interface handles:

• Job distribution — receiving work from the control board
• Nonce reporting — sending back valid solutions
• Register access — reading and writing chip configuration registers (PLL settings, voltage trim, chip address, etc.)
• Chain forwarding — passing data to the next chip in the daisy chain

Voltage Regulation Interface

Modern mining ASICs include on-die voltage sensing and sometimes voltage trim circuitry. The chip can report its internal voltage and temperature to the control board, enabling closed-loop voltage optimization. Some generations include configurable voltage offset registers that allow fine-tuning without external hardware changes.

Temperature Sensor

An on-die temperature sensor (typically a bandgap reference-based circuit) reports junction temperature. This reading is critical for thermal management — the control board uses it to adjust fan speed, throttle frequency, or shut down the chip if it exceeds safe operating limits (typically 105-125 degrees C junction temperature).

Voltage and Frequency Relationship

The relationship between voltage, frequency, and power is the single most important concept for understanding ASIC chip performance and efficiency.

The V/F Curve

Every digital circuit has a minimum voltage required to operate reliably at a given frequency. This relationship is known as the voltage-frequency (V/F) curve:

Frequency (MHz)
    ^
800 |                    ___________
    |                 __/
700 |              __/
    |           __/
600 |        __/
    |     __/
500 |  __/
    | /
400 |/
    +-----|-----|-----|-----|------> Voltage (V)
         0.20  0.25  0.30  0.35

At lower voltages, the transistors switch more slowly, limiting the maximum stable frequency. Raising voltage allows faster switching, enabling higher clock speeds — but the relationship is not linear for power.

The Power Equation

Dynamic power consumption in a CMOS circuit follows this fundamental equation:

P = C * V^2 * f * N

Where:

• P = power consumption (watts)
• C = capacitance (determined by die area and process node)
• V = supply voltage
• f = clock frequency
• N = number of active transistors switching per cycle

The critical insight is that power scales with the square of voltage. This means:

Efficiency Sweet Spot

Every chip has an efficiency sweet spot — the voltage/frequency combination that minimizes joules per terahash (J/TH). This point is typically well below the chip's maximum frequency capability.

For example, a hypothetical chip might have:

Silicon Lottery

Not all chips are created equal. Manufacturing variation means that two chips from the same wafer can have different V/F characteristics. A "good" chip can reach 600 MHz at 0.27V, while a "bad" chip from the same batch might need 0.30V for the same frequency. This variation is called the silicon lottery, and it is why:

• Some hash boards consistently perform better than others
• Auto-tuning per-chip is more efficient than blanket voltage settings
• Chip binning (sorting by quality) is a key part of the manufacturing process

Power Efficiency Metrics

Efficiency in mining is measured in joules per terahash (J/TH) — the amount of energy consumed to compute one trillion hashes. Lower is better.

Understanding J/TH

J/TH = Power (watts) / Hashrate (TH/s)

Since 1 watt = 1 joule per second, J/TH directly tells you how many joules of electrical energy are consumed per terahash of computation. At the wall, you also need to account for PSU efficiency (typically 90-95% for platinum-rated supplies) and ancillary loads (fans, control board).

Real-World Efficiency by Generation

What Drives Efficiency Improvement

Three factors drive J/TH improvements across chip generations:

1. Process node shrink — Moving from 16nm to 7nm to 5nm to 3nm reduces transistor size, lowering capacitance (C in the power equation) and enabling lower operating voltages.

2. Architectural optimization — Better pipeline design, improved clock tree distribution, and more efficient adder circuits reduce the energy per hash operation.

3. Voltage reduction — Each generation typically operates at a lower core voltage. Since power scales with V-squared, even small voltage reductions yield significant efficiency gains.

Chip Evolution: BM1387 to BM1370

Bitmain's chip lineup tells the story of mining ASIC evolution. Each generation brought improvements in process technology, efficiency, or both.

The Bitmain Chip Family

Generation-by-Generation Breakdown

How Chips Communicate

Mining ASIC chips on a hash board do not operate independently — they are connected in a daisy chain and communicate with the control board through a serial protocol. Understanding this communication architecture is essential for diagnosing "missing chip" errors and communication failures.

The Daisy Chain

Chips are connected in series, with data flowing from the control board through each chip sequentially:

Control Board
    |
    | TX (UART)
    v
[Chip 0] --CI/CO--> [Chip 1] --CI/CO--> [Chip 2] ---> ... ---> [Chip N]
[Chip 0] <--RI/RO-- [Chip 1] <--RI/RO-- [Chip 2] <--- ... <--- [Chip N]
    |
    | RX (UART)
    v
Control Board

Signal Lines

Each chip has four key communication pins:

In Bitmain's newer chips, CI/CO carry the UART TX signal (commands flowing from control board to chips), while RI/RO carry the UART RX signal (responses flowing from chips back to the control board).

Communication Protocol

Baud Rate and Timing

Different chip generations operate at different default UART baud rates:

The BO (Break Out) Signal

Some Bitmain chips include a BO (Break Out) pin. When a chip detects an internal fault, it asserts BO, which can trigger a bypass circuit on the hash board to route communication around the failed chip. This feature is not universally implemented across all board designs, but when present, it improves chain resilience.

Common Chip Failures

ASIC chips fail in predictable ways. Understanding these failure modes helps you diagnose problems faster and determine whether a chip needs replacement or whether the root cause lies elsewhere on the board.

1. Short Circuits (VDD to VSS)

A chip with an internal short between the power rail (VDD) and ground (VSS) will drag down the entire voltage domain it belongs to. Symptoms include:

• Domain voltage reads near zero or significantly below target
• Multiple chips in the same domain report as missing (they are all underpowered)
• Excessive current draw on that domain's power rail
• Thermal hotspot — the shorted chip may get extremely hot even at low voltage

Diagnosis: Use a thermal camera or measure domain voltages. A domain with a shorted chip will have abnormally low voltage. You can sometimes identify the specific chip by measuring resistance between VDD and VSS pads with the board unpowered.

2. Open Circuits (Broken Solder Joints)

BGA-packaged chips (BM1366, BM1368, BM1370) can develop open solder joints — where one or more solder balls lose connection to the PCB pad. This can be caused by thermal cycling, mechanical stress, or manufacturing defects.

Symptoms depend on which balls are affected:

• Power balls open: Chip appears dead (no response to communication)
• CI/CO or RI/RO balls open: Chain break — all downstream chips missing
• Partial power open: Intermittent errors, chip works sometimes, fails under load

Diagnosis: Gentle pressure on the chip with a probe while the board is running can sometimes temporarily restore connection, confirming a BGA joint issue. Definitive repair requires BGA rework — removing the chip, reballing, and resoldering.

3. Thermal Damage

ASIC chips are rated for junction temperatures up to 105-125 degrees C, but sustained operation near these limits degrades the silicon over time. Electromigration — the physical movement of metal atoms in the chip's interconnects due to high current density — accelerates at elevated temperatures.

Thermal damage manifests as:

• Gradually increasing error rate over weeks/months
• Chip eventually stops responding entirely
• No visible external damage (the failure is internal to the silicon)

Prevention: Adequate cooling, clean heatsinks, proper thermal paste application, and avoiding operation above rated temperatures. See Cooling and Thermal Management.

4. ESD (Electrostatic Discharge) Damage

ASIC chips operate at very low voltages (0.25-0.40V). An electrostatic discharge of even a few hundred volts — far below what a human can feel — can destroy the thin gate oxide of the chip's transistors.

ESD damage is insidious because:

• It can cause latent damage that does not manifest immediately but causes premature failure weeks later
• There is no visible indication of ESD damage externally
• A single touch without proper grounding can destroy a chip worth $10-50

5. Overvoltage Damage

If a voltage regulator fails or is misconfigured, it can supply voltage above the chip's maximum rating. Even a brief overvoltage event can permanently damage the gate oxide across an entire domain of chips.

Common causes:

• Failed buck converter MOSFET (stuck on)
• Incorrect firmware voltage setting during manual tuning
• Power supply voltage spike during startup or shutdown

Failure Summary Table

Key Takeaways

1. ASICs dominate mining because they eliminate all general-purpose overhead. Every transistor serves SHA-256 computation, yielding 3,000x better efficiency than GPUs.

2. The SHA-256 pipeline is implemented as fixed combinational logic — no software, no instructions, just hardwired gates computing 64 rounds of compression per hash.

3. Power scales with V-squared, meaning voltage reduction is the most powerful lever for improving efficiency. This is why each chip generation targets lower operating voltages.

4. J/TH is the key metric for mining economics. The industry has improved from 96 J/TH (BM1387, 16nm, 2016) to 15 J/TH (BM1370, 3nm, 2024) — a 6.4x improvement in eight years.

5. Daisy chain communication means a single failed chip can take out the entire downstream chain. This is the most common cause of "missing chips" errors.

6. Chip failures are predictable — shorts, opens, thermal damage, and ESD account for the vast majority of issues. Proper diagnostics start with understanding what each failure looks like.

Apply This Knowledge

Now that you understand how ASIC mining chips work at a fundamental level, here is how to put this knowledge into practice: