BM1368 ASIC Chip

Overview

The BM1368 is Bitmain's 5nm SHA-256 mining ASIC designed for the Antminer S21 and T21 product lines. It represents a full generational leap from the BM1366 used in the S19 XP, delivering approximately 17.5 J/TH — a substantial improvement that cemented the S21 as one of the most efficient air-cooled miners available at launch.

The BM1368 uses an advanced 5nm process with optimized standard cell libraries and a redesigned power distribution network on-die. Bitmain increased the number of hashing cores per chip while simultaneously lowering the per-core operating voltage, resulting in a net efficiency gain even at higher aggregate hashrates. The chip retains the familiar daisy-chain communication protocol used across the BM13xx family, ensuring firmware and tooling compatibility.

Each S21 hashboard contains 156 BM1368 chips organized into 12 voltage domains with 13 chips per domain. This domain structure allows fine-grained voltage tuning — the controller can adjust each domain's supply independently to optimize the power-performance tradeoff across the board, compensating for silicon variation between individual chips.

The BM1368's thermal design power is managed through direct contact between the BGA package backside and a precision-machined aluminum heatsink. The S21 platform uses improved thermal interface materials compared to earlier generations, which is critical given the higher power density of the 5nm process.

Specifications

Pin Configuration

The BM1368 uses a BGA package with an updated ball map compared to its 7nm predecessors. While the communication protocol remains compatible, the power delivery pins have been reorganized to support the lower core voltage with higher current capacity.

Power Pins

• VDD — Core power supply (0.30V nominal). The BM1368 draws higher current per chip than the BM1366 despite the lower voltage, reflecting the increased core count. Buck converters must provide very clean power with minimal ripple — the 5nm process is less tolerant of voltage noise.
• VDDIO — I/O power supply (1.8V). Powers the serial communication transceivers and PLL analog circuits.
• VSS — Ground. The BM1368 has additional ground balls compared to the BM1366 to reduce package inductance and improve power integrity.

Communication Pins

• CI — Clock Input from the upstream chip or controller.
• CO — Clock Output to the downstream chip.
• RI — Receive Input (serial data from upstream).
• RO — Receive Output (serial data to downstream).
• BO — Break Out fault indication signal.

PLL Pins

• XCLK — External clock reference (25 MHz typical). The BM1368's PLL supports a wider frequency range than previous generations, enabling both the high-performance S21 and the efficiency-tuned T21 from the same silicon.

// PLL frequency register configuration for BM1368
// The BM1368 uses an updated PLL encoding
#define BM1368_PLL_FREQ_500M  0x00C0286401
#define BM1368_PLL_FREQ_550M  0x00C02C6401
#define BM1368_PLL_FREQ_600M  0x00C0306401
#define BM1368_PLL_FREQ_650M  0x00C0346401
#define BM1368_PLL_FREQ_700M  0x00C0386401

Common Failure Modes

1. Dead Chip (No Enumeration Response)

The chip fails to respond during the initial chain enumeration sequence. Because the BM1368 uses a 13-chip domain structure, a single dead chip can mask the remaining chips downstream in its chain segment.

Diagnosis:

• Measure VDD at the chip's power pads. Expected: 0.30V ±8mV. A reading of 0V suggests an upstream power fault; a reading significantly below nominal may indicate a short on the chip die.
• Check BO pin state. If the chip pulls BO low, it has detected an internal fault condition.
• Probe CI/RI signals at the suspect chip. If signals are present at CI/RI but absent at CO/RO, the chip is dead and breaking the chain.

Root causes: ESD damage during handling, voltage regulator failure causing overvoltage, thermal runaway from inadequate heatsink contact, or infant mortality (early-life failure of 5nm die).

2. Domain Voltage Instability

The entire voltage domain containing the chip oscillates or fails to regulate. The S21's domain controller reports voltage faults and may shut down the domain.

Diagnosis:

• Measure the domain bus voltage with an oscilloscope. Look for oscillation, excessive droop under load, or failure to reach the target voltage.
• A single shorted chip in the domain pulls down the entire bus. Disconnect chips one at a time (by reflowing and removing) to isolate the faulty device.
• Check the domain's buck converter output capacitors and inductors for damage.

3. High Hardware Error Rate

The chip enumerates successfully but returns an elevated number of invalid nonces. This can indicate partial core failure or marginal operating conditions.

Diagnosis:

• Compare HW error rates across chips in the same domain. If one chip is significantly worse, it likely has partial core damage.
• Check core voltage stability — ripple above 15mV peak-to-peak at 5nm can cause timing faults.
• Verify PLL lock status. An intermittently unlocked PLL produces bursts of errors.

4. Thermal Throttling

The BM1368's 5nm process packs more hashing power into each chip, making thermal management critical. Chips that exceed their thermal limit will throttle or shut down.

Diagnosis:

• Use thermal imaging to identify chips running more than 8°C above the board average.
• Inspect thermal paste coverage — the BM1368 BGA package must have full, even coverage with no voids.
• Verify fan speed and airflow path. The S21 uses a specific airflow design; blocked intake or exhaust vents cause localized hot spots.

Replacement Procedure

For detailed BGA rework techniques, see the BGA Rework Guide.

Found In These Miners

Compare With

• BM1366 — Previous 5nm generation, used in S19 XP. ~21.5 J/TH efficiency.
• BM1370 — Next generation for S21 Pro. Even higher efficiency at ~15 J/TH.
• BM1362 — 7nm chip used in S19j Pro. Different process node and power characteristics.
• BM1398 — Legacy 7nm chip from the original S19 line.

Further Reading

• ASIC Chip Architecture
• Voltage Domains & Regulators
• Clock Distribution & PLL
• Cooling & Thermal Management
• ASIC Chip Comparison