Clock Distribution and PLL in Mining ASICs

Introduction

Every computation inside an ASIC chip happens in lockstep with a clock signal. Without a stable, precisely timed clock, the billions of SHA-256 hash attempts per second that make mining profitable would be impossible. The clock distribution system on a hash board is responsible for generating, multiplying, and delivering that timing signal to every chip in the chain.

This article explains how clock signals originate from a crystal oscillator, how each chip's internal Phase-Locked Loop (PLL) multiplies that reference into a high-speed core clock, how the clock propagates across dozens of chips, and what happens when things go wrong.

Understanding clock distribution is essential for diagnosing some of the trickiest hash board failures — from entire boards going dark to intermittent hash errors that defy easy explanation.

Clock Sources in Mining Hardware

The Crystal Oscillator

At the start of every hash board's clock tree sits a crystal oscillator — a small, four-pin component that generates a stable reference frequency. In virtually all Bitmain hash boards (S19 series through S21), this is a 25 MHz crystal oscillator.

The crystal oscillator works by exploiting the piezoelectric properties of quartz. When voltage is applied, the quartz crystal vibrates at a precise mechanical resonance frequency. This vibration is converted back into an electrical signal — a clean, stable 25 MHz square wave.

Why 25 MHz? This frequency is a widely available industry standard that offers a good balance: high enough to serve as a useful reference, low enough to propagate reliably across PCB traces without significant signal integrity concerns, and easily multiplied by PLLs to reach the 400–800 MHz range that ASIC cores need.

Why a Reference Clock is Needed

ASIC chips cannot generate their own precise clock internally. While ring oscillators and RC oscillators exist, they drift with temperature and voltage — sometimes by 10% or more. A crystal oscillator provides:

• Accuracy: typically within ±50 ppm (parts per million) of the target frequency
• Stability: minimal drift across the operating temperature range (0–85°C)
• Low jitter: clean edges that PLLs can lock onto reliably

Clock Input Pin (XCLK / CLKI)

The crystal oscillator's output connects to the first chip in the daisy chain via its clock input pin, commonly labeled XCLK or CLKI in datasheets. From there, the clock propagates chip-to-chip through the CI/CO (Clock In / Clock Out) chain.

PLL Operation Explained

What is a PLL?

A Phase-Locked Loop (PLL) is a feedback control circuit that generates a high-frequency output signal synchronized to a low-frequency reference input. Every ASIC mining chip — BM1366, BM1368, BM1370, BM1398, and others — contains one or more on-chip PLLs.

The PLL's job is to take the 25 MHz reference and multiply it up to the chip's core operating frequency, typically 400–800 MHz depending on the chip model and firmware configuration.

PLL Block Diagram

A PLL consists of four fundamental blocks:

                    ┌─────────────────────────────────┐
  Reference         │           PLL Circuit            │
  25 MHz ──────►┌──────────┐    ┌──────────┐    ┌─────┐│    Core Clock
                │  Phase   │    │   Loop   │    │     ││───► 400-800 MHz
                │ Detector ├───►│  Filter  ├───►│ VCO ││
                └────▲─────┘    └──────────┘    └──┬──┘│
                     │                             │    │
                     │    ┌──────────────┐         │    │
                     └────┤   Feedback   │◄────────┘    │
                          │   Divider    │              │
                          │   (÷N)       │              │
                          └──────────────┘              │
                    └─────────────────────────────────┘

Lock Time and Stability

When a PLL is first enabled or its frequency is changed, it takes time to lock — to stabilize at the target frequency. This lock time is typically 50–200 microseconds for mining ASICs. During lock-up, the output clock is unstable and the chip should not be performing hashing work.

Firmware initialization sequences account for this by inserting delays after PLL configuration:

// After writing PLL registers, wait for lock
bm1366_set_pll(chain, chip_addr, target_freq);
vTaskDelay(pdMS_TO_TICKS(5));  // 5ms — generous margin over ~100µs lock time

A PLL that cannot lock — due to a missing reference clock, insufficient supply voltage, or silicon defect — will cause the chip to either not respond at all or produce erratic, useless output.

PLL Configuration in Bitmain ASIC Chips

Register-Based Frequency Setting

Bitmain ASIC chips expose PLL configuration through memory-mapped registers accessible via the serial command interface. The firmware writes specific register values during chip initialization to set each chip's core frequency.

The PLL register encodes several fields:

• FBDIV (Feedback Divider): the main multiplication factor
• REFDIV (Reference Divider): divides the input reference before the phase detector
• POSTDIV1 / POSTDIV2 (Post-Dividers): divide the VCO output after the PLL loop

The effective output frequency is calculated as:

f_out = (f_ref × FBDIV) / (REFDIV × POSTDIV1 × POSTDIV2)

For a 25 MHz reference targeting 500 MHz with REFDIV=1, POSTDIV1=1, POSTDIV2=1:

FBDIV = 500 / 25 = 20
f_out = (25 × 20) / (1 × 1 × 1) = 500 MHz

BM1366 and BM1368 PLL Registers

// BM1366 PLL frequency presets
// Format: { reg_addr_hi, reg_addr_lo, data[0], data[1], data[2] }

// 400 MHz: FBDIV=16, REFDIV=1, POSTDIV1=1, POSTDIV2=1
static const uint8_t pll_400mhz[] = { 0x00, 0xF0, 0x20, 0x64, 0x01 };

// 500 MHz: FBDIV=20, REFDIV=1, POSTDIV1=1, POSTDIV2=1
static const uint8_t pll_500mhz[] = { 0x00, 0xF0, 0x28, 0x64, 0x01 };

// 600 MHz: FBDIV=24, REFDIV=1, POSTDIV1=1, POSTDIV2=1
static const uint8_t pll_600mhz[] = { 0x00, 0xF0, 0x30, 0x64, 0x01 };

// 700 MHz: FBDIV=28, REFDIV=1, POSTDIV1=1, POSTDIV2=1
static const uint8_t pll_700mhz[] = { 0x00, 0xF0, 0x38, 0x64, 0x01 };

// BM1366 PLL initialization — set all chips to 500 MHz
void bm1366_init_pll(uint8_t chain_id) {
    // PLL register write command (CMD_WRITE_REG = 0x41)
    uint8_t cmd[] = {
        0x55, 0xAA,           // Preamble
        0x51, 0x09,           // Header: all-chip, length=9
        0x41,                 // CMD_WRITE_REG
        0x00, 0x00,           // Chip address (0x0000 = broadcast)
        0x00, 0xF0,           // Register: PLL0
        0x28, 0x64, 0x01,     // PLL data: 500 MHz
        0x00                  // CRC placeholder
    };
    uart_write(chain_id, cmd, sizeof(cmd));

    // Wait for PLL lock across all chips
    vTaskDelay(pdMS_TO_TICKS(10));
}

// BM1368 PLL frequency presets
// The BM1368 supports finer granularity via fractional dividers

// 400 MHz
static const uint8_t pll_400mhz[] = { 0x00, 0xF0, 0x20, 0x64, 0x01 };

// 500 MHz
static const uint8_t pll_500mhz[] = { 0x00, 0xF0, 0x28, 0x64, 0x01 };

// 525 MHz (typical S21 stock frequency)
static const uint8_t pll_525mhz[] = { 0x00, 0xF0, 0x2A, 0x64, 0x01 };

// 600 MHz (overclocked)
static const uint8_t pll_600mhz[] = { 0x00, 0xF0, 0x30, 0x64, 0x01 };

// Set chip 15 to a lower frequency (450 MHz) due to thermal hotspot
void bm1368_tune_chip(uint8_t chain_id, uint8_t chip_index) {
    uint16_t chip_addr = chip_index * chip_addr_interval;
    uint8_t cmd[] = {
        0x55, 0xAA,
        0x41, 0x09,
        0x41,                       // CMD_WRITE_REG
        (chip_addr >> 8) & 0xFF,    // Chip address high
        chip_addr & 0xFF,           // Chip address low
        0x00, 0xF0,                 // Register: PLL0
        0x24, 0x64, 0x01,           // PLL data: 450 MHz
        0x00                        // CRC
    };
    uart_write(chain_id, cmd, sizeof(cmd));
}

Post-Divider Configuration

The post-dividers (POSTDIV1, POSTDIV2) provide additional flexibility. Instead of running the VCO at exactly the target frequency, the VCO can run at a higher frequency within its optimal range and be divided down:

Example: Targeting 200 MHz
  Option A: VCO at 200 MHz (may be below VCO optimal range)
  Option B: VCO at 800 MHz, POSTDIV1=2, POSTDIV2=2 → 800/4 = 200 MHz (better)

The firmware must account for this difference:

// Post-divider encoding differs by chip model
uint8_t encode_postdiv(uint16_t chip_model, uint8_t divider) {
    switch (chip_model) {
        case 0x1398:  // BM1398
            return divider;           // Raw value
        case 0x1366:  // BM1366
        case 0x1368:  // BM1368
        case 0x1370:  // BM1370
            return divider - 1;       // Minus one encoding
        default:
            return divider;
    }
}

Frequency Ramping During Initialization

Production firmware does not jump directly to the target frequency. Instead, it ramps the PLL frequency in steps to avoid voltage droops caused by sudden current spikes:

// Gradual PLL ramp-up during initialization
void bm1366_ramp_pll(uint8_t chain_id, uint16_t target_mhz) {
    uint16_t steps[] = { 200, 300, 400, 0 };  // Intermediate steps

    for (int i = 0; steps[i] != 0 && steps[i] < target_mhz; i++) {
        bm1366_set_pll_freq(chain_id, BM_ADDR_BROADCAST, steps[i]);
        vTaskDelay(pdMS_TO_TICKS(10));  // Settle time between steps
    }

    // Final target
    bm1366_set_pll_freq(chain_id, BM_ADDR_BROADCAST, target_mhz);
    vTaskDelay(pdMS_TO_TICKS(20));  // Longer settle at final frequency
}

This ramping is visible in logic analyzer captures of the initialization sequence — you can see multiple PLL register writes spaced a few milliseconds apart with increasing FBDIV values.

Frequency and Hashrate Relationship

The Linear Relationship

The relationship between clock frequency and hashrate is approximately linear: doubling the core frequency roughly doubles the hash rate. Each clock cycle, the hashing cores complete one step of the SHA-256 pipeline. More cycles per second means more hashes per second.

Hashrate ∝ Frequency × Number_of_Cores

Example (BM1366):
  At 500 MHz: ~52 TH/s per chip (estimated)
  At 600 MHz: ~62 TH/s per chip (estimated)
  At 700 MHz: ~73 TH/s per chip (estimated)

The Power Problem: V²×f

While hashrate scales linearly with frequency, power consumption does not. Dynamic power in CMOS circuits follows:

P_dynamic = C × V² × f

Where:
  C = capacitance (fixed by chip design)
  V = supply voltage
  f = clock frequency

Higher frequencies require higher voltages for reliable switching. The relationship between frequency and required voltage is roughly linear in the operating range, which means:

• Power scales approximately as f³ (since V scales with f, and P ∝ V² × f)
• Going from 500 MHz to 700 MHz (1.4× frequency) can increase power by ~2.7× (1.4³)
• Energy efficiency (J/TH) degrades rapidly at higher frequencies

The Efficiency Sweet Spot

Every chip has a frequency range where the joules per terahash (J/TH) metric is minimized. This is the sweet spot where you get the most hashing per watt of electricity consumed.

Clock Tree on a Hash Board

Crystal to First Chip

The clock distribution starts with the crystal oscillator and propagates through the entire chain of chips:

Crystal       Chip 0        Chip 1        Chip 2              Chip N
  OSC ──────► CLKI → PLL   CLKI → PLL   CLKI → PLL          CLKI → PLL
              CLKO ────────► ↑    CLKO ────────► ↑              ↑
                                                    ...  ────────┘

CI/CO Signal Characteristics

The CI (Clock In) and CO (Clock Out) signals on Bitmain hash boards are typically:

• Voltage level: 1.8V LVCMOS or 0.8V differential (varies by generation)
• Frequency: 25 MHz reference (not the multiplied core clock)
• Rise/fall time: ~2 ns typical
• Trace impedance: 50 ohm controlled impedance on well-designed boards

Clock Jitter Accumulation

Every time the clock signal passes through a chip's clock buffer (CLKI → CLKO), a small amount of jitter is added. Jitter is the variation in the timing of clock edges — the clock edge arrives slightly early or late compared to the ideal position.

After passing through many chips, this accumulated jitter can become significant:

Jitter per chip:    ~5-15 ps RMS (typical for modern ASICs)
After 50 chips:     ~35-106 ps RMS (jitter adds as √N)
After 100 chips:    ~50-150 ps RMS
After 150 chips:    ~61-184 ps RMS

At 25 MHz, one clock period is 40 ns (40,000 ps), so even 200 ps of jitter is only 0.5% of the period — well within tolerance. However, the PLL inside each chip amplifies jitter relative to the multiplication factor. At 500 MHz (20× multiplication), 200 ps of input jitter could contribute to ~200 ps of output jitter, and one period is only 2 ns (2,000 ps). This is why clock jitter matters more for chips at the end of long chains.

Overclocking and Underclocking

How Custom Firmware Adjusts Frequency

Custom firmware solutions provide granular control over PLL frequencies:

Overclocking: Risks and Rewards

Increasing PLL frequency beyond stock settings trades efficiency for higher hashrate:

Rewards:

• Higher total hashrate from existing hardware
• Can be profitable when Bitcoin price is high relative to electricity cost

Risks:

• Increased power consumption (non-linear — see V²×f above)
• Higher operating temperatures, potentially exceeding thermal limits
• Elevated hash error rates, reducing effective hashrate
• Accelerated electromigration and chip degradation
• Risk of power delivery failure if voltage regulators are pushed beyond design margins

Underclocking: The Efficiency Play

Reducing PLL frequency below stock settings is increasingly popular among miners focused on efficiency:

• 10-20% frequency reduction can yield 30-40% power savings (due to voltage reduction)
• Lower temperatures extend component lifespan
• Fewer hash errors mean more consistent effective hashrate
• Quieter operation from reduced fan speeds
• Particularly attractive in regions with higher electricity costs

// Example: Underclocking a BM1368 from 525 MHz stock to 425 MHz
// Power reduction: ~40%, Hashrate reduction: ~19%, Efficiency gain: ~25%
bm1368_set_pll_freq(chain_id, BM_ADDR_BROADCAST, 425);
bm1368_set_core_voltage(chain_id, 0.265);  // Lower voltage matches lower freq

Diagnosing Clock-Related Issues

Clock problems manifest in distinct patterns that help narrow the diagnosis.

Symptom: All Chips Missing

Cause: No reference clock reaching the first chip.

When the crystal oscillator fails or its output trace is broken, no chip on the board receives a clock. Without a clock, the chips' PLLs cannot lock and the chips cannot respond to commands.

Diagnosis:

1. Use an oscilloscope to probe the crystal oscillator output — you should see a clean 25 MHz square wave
2. Probe the CLKI pin of Chip 0 — signal should be present
3. Check for physical damage to the crystal oscillator or surrounding passives

Expected: Clean 25 MHz square wave, 1.8V amplitude, <2 ns rise time
Failure:  No signal, DC level, or severely distorted waveform

Symptom: Intermittent Hash Errors

Cause: Clock jitter, marginal PLL lock, or power supply noise.

When the clock signal is present but degraded, PLLs may lock intermittently or with excessive jitter. The core clock will have timing violations that cause occasional computational errors.

Diagnosis:

1. Check error rates per chip — if errors correlate with chain position (worse toward the end), jitter accumulation is likely
2. Probe CI/CO signals at the problem chip — look for reduced amplitude, slow edges, or ringing
3. Check power supply ripple on the chip's VDD — excessive ripple couples into the PLL

Symptom: Partial Chain Loss

Cause: Clock break at a specific chip in the chain.

If Chip N's CLKO fails, all chips from N+1 onward lose their clock reference. The firmware will see chips 0 through N responding normally and all subsequent chips missing.

Diagnosis:

1. Identify the last responding chip — call it Chip N
2. Probe Chip N's CLKO pin — if absent or distorted, Chip N's clock output circuit is damaged
3. Probe Chip N+1's CLKI pin to confirm the signal is not arriving
4. Common causes: cold solder joint on CLKO/CLKI pin, damaged chip, broken PCB trace

Control Board → Chip 0 ✓ → Chip 1 ✓ → ... → Chip N ✓ → Chip N+1 ✗ → ... → Chip M ✗
                                                  │
                                           CLKO failure here

Testing with an Oscilloscope

An oscilloscope is the definitive tool for clock diagnostics. Key measurement points:

Recommended oscilloscope settings for clock measurement:

• Bandwidth: 200 MHz minimum (10× the fundamental for edge quality)
• Timebase: 10-20 ns/div to see individual clock cycles
• Trigger: rising edge on the channel being measured
• Probe: 10:1 passive probe, properly compensated

For jitter measurements, use the oscilloscope's histogram or persistence mode on the clock edges. Normal jitter should appear as a tight distribution; problematic jitter will show broad, sometimes bimodal distributions.

See Oscilloscope Basics for Miners for a complete guide to oscilloscope operation.

Key Takeaways

1. The crystal oscillator is the clock source for the entire hash board — a single 25 MHz reference that every chip depends on.

2. PLLs multiply the reference clock from 25 MHz up to 400–800 MHz using feedback divider registers controlled by firmware.

3. PLL registers are chip-specific — the BM1366, BM1368, and other models use register-based frequency configuration with subtle encoding differences (especially post-divider encoding).

4. Frequency and hashrate are linearly related, but power scales much faster than frequency (approximately V²×f), creating a clear efficiency sweet spot.

5. Clock propagates chip-to-chip via the CI/CO daisy chain, with each chip regenerating the reference for the next. Jitter accumulates along the chain.

6. Custom firmware enables per-chip tuning — overclocking for maximum hashrate or underclocking for maximum efficiency.

7. Clock failures produce distinctive patterns: all chips missing (crystal failure), intermittent errors (jitter/instability), or partial chain loss (mid-chain clock break).

Apply This Knowledge

Now that you understand clock distribution and PLL operation, explore these related topics:

• How Hash Boards Work — the broader context of hash board architecture
• Signal Integrity Basics — understanding signal quality, reflections, and impedance matching
• Voltage Domains & Regulators — how power delivery interacts with clock frequency
• Oscilloscope Basics for Miners — hands-on measurement techniques for clock signals
• Auto-Tuning Explained — how firmware automatically optimizes per-chip frequencies
• UART, SPI & I2C Explained — the communication protocols used alongside clock distribution