BM1362 ASIC Chip

Overview

The BM1362 is a SHA-256 mining ASIC manufactured by Bitmain, introduced as an improved 7nm design for the Antminer S19j Pro and S19j Pro+ series. It builds on the foundation of the BM1398 with optimizations to the core hashing engine and power delivery network, achieving better energy efficiency at comparable clock speeds. The BM1362 was Bitmain's bridge chip between the original S19 generation and the later 5nm designs like the BM1366.

Where the BM1398 powered the first wave of S19 miners at roughly 30 J/TH, the BM1362 brought that figure down to approximately 24.5 J/TH through improved transistor-level layout and tighter voltage regulation requirements. This made the S19j Pro series one of the most popular miners for operators seeking a balance between hashrate, efficiency, and upfront cost.

The chip uses Bitmain's standard daisy-chain communication protocol, where chips are connected in series via CI/CO (clock) and RI/RO (data) signal pairs. Each chip is individually addressable after enumeration, and the controller communicates job assignments and reads back nonces through this serial chain.

Specifications

Pin Configuration

The BM1362 uses a BGA (Ball Grid Array) package with a pin layout largely compatible with the BM1398 family, though the internal die is a revised 7nm design. Key signal groups include:

Power Pins

• VDD — Core power supply (0.32V nominal). Fed by per-domain buck converters on the hashboard. Each voltage domain typically powers a group of chips in series, and the BM1362 requires tight regulation (±3%) for stable hashing.
• VDDIO — I/O power supply (1.8V). Shared across the communication bus and used by the CI/CO/RI/RO transceivers.
• VSS — Ground. Multiple ground pads provide low-impedance return paths and thermal dissipation through the BGA substrate.

Communication Pins

• CI — Clock Input. Receives the clock signal from the previous chip in the chain (or from the FPGA/controller for the first chip).
• CO — Clock Output. Passes the clock to the next chip in the daisy chain.
• RI — Receive Input. Serial data input from the upstream chip or controller.
• RO — Receive Output. Serial data output to the downstream chip.
• BO — Break Out signal. Active when the chip detects an internal fault. The controller monitors BO to identify failed chips in the chain without requiring full enumeration.

PLL Pins

• XCLK — External clock reference input. The on-chip PLL multiplies this reference to generate the core hashing clock. Typical reference is 25 MHz.

// PLL frequency register configuration for BM1362
// Uses similar encoding to BM1366 family
// Target: 500 MHz core clock
#define BM1362_PLL_FREQ_500M  0x00F0286401
#define BM1362_PLL_FREQ_550M  0x00F02C6401
#define BM1362_PLL_FREQ_600M  0x00F0306401
#define BM1362_PLL_FREQ_650M  0x00F0346401

Common Failure Modes

1. Dead Chip (No Response During Enumeration)

The most common failure. The chip does not respond when the controller sends enumeration commands down the chain. Symptoms include a reduced chip count reported by the miner firmware and a corresponding drop in hashrate.

Diagnosis:

• Measure VDD at the suspect chip's power pads. Expected: 0.32V ±10mV under load. If absent or significantly low, the fault may be in the upstream buck converter or a short on the chip itself.
• Check the BO signal. If BO is asserted (pulled low), the chip has detected an internal fault.
• Probe CI/CO continuity. A dead chip breaks the daisy chain, so all chips downstream of it will also be unreported.

Root causes: Electrical overstress from power supply transients, solder joint fatigue from thermal cycling, manufacturing defects, or lightning-induced surges through the PSU.

2. Low Hashrate / High HW Error Rate

The chip responds to enumeration but produces fewer valid nonces than expected, or a high proportion of returned nonces fail validation.

Diagnosis:

• Check PLL lock status via register read. An unlocked PLL means the chip is hashing at the wrong frequency.
• Monitor core voltage ripple with an oscilloscope. Excessive ripple (>20mV peak-to-peak) causes timing violations in the hash cores.
• Compare the chip's nonce rate against its neighbors in the same domain. A chip producing less than 70% of the expected rate likely has partial core failure.

3. Thermal Failure

The chip overheats beyond its rated junction temperature, causing intermittent resets or permanent damage. The BM1362 at 7nm generates significant heat density.

Diagnosis:

• Use a thermal camera to identify hot spots on the hashboard. A chip running 10°C or more above its neighbors indicates poor thermal contact.
• Inspect the thermal interface material (TIM) between the chip and heatsink. Dried-out or displaced thermal paste is the most common cause.
• Check airflow. Blocked fans or clogged heatsink fins reduce cooling capacity.

4. Chain Break (Downstream Chips Missing)

A partially failed BM1362 may corrupt the CO/RO signals, causing all downstream chips to become unreachable. The chip itself may still respond, but the data it forwards is garbled.

Diagnosis:

• If the chain breaks at a consistent chip position, probe the CO and RO signals at that chip with an oscilloscope. Look for proper signal levels (0V/1.8V transitions) and correct baud rate.
• Swap the suspect chip and retest. If the break point moves, the original chip was at fault.

Replacement Procedure

Replacing a BM1362 requires BGA rework equipment and experience with fine-pitch BGA soldering:

For detailed BGA rework techniques, see the BGA Rework Guide.

Found In These Miners

• Antminer S19j Pro — 104 TH/s, ~126 chips per hashboard, 3 hashboards per unit. Released mid-2021 as a cost-optimized alternative to the original S19 Pro.
• Antminer S19j Pro+ — 120 TH/s, higher clock configuration of the same BM1362 chip with improved board-level power delivery.

Compare With

• BM1398 — Previous generation 7nm chip, used in S19/S19 Pro. Lower efficiency (~30 J/TH) but widely available.
• BM1366 — 5nm chip used in S19 XP. Significant efficiency jump over the BM1362.
• BM1368 — Next-generation 5nm chip for the S21 series.

Further Reading

• ASIC Chip Architecture
• Voltage Domains & Regulators
• Clock Distribution & PLL
• ASIC Chip Comparison