BM1370 ASIC Chip

Overview

The BM1370 is Bitmain's most advanced SHA-256 mining ASIC as of 2024–2025, built on an advanced 5nm process node. It powers the Antminer S21 Pro and S21 XP — the highest-efficiency Bitcoin miners in Bitmain's product lineup, achieving approximately 15 J/TH at the system level.

The BM1370 represents the culmination of Bitmain's iterative optimization strategy: each generation refines the hashing core microarchitecture, power delivery network, and PLL design within the same 5nm process family. Compared to the BM1368, the BM1370 achieves its efficiency gains primarily through a lower operating voltage (0.27V vs 0.30V) and improved core utilization, where more of the die area is dedicated to active hashing engines rather than support logic.

The chip maintains backward compatibility with Bitmain's daisy-chain communication protocol. However, the S21 Pro and S21 XP boards use updated control board firmware that takes advantage of new BM1370-specific register fields for finer-grained power management and per-chip performance monitoring. This means that while the protocol is compatible, BM1370 boards cannot be used interchangeably with BM1368 boards in the same chassis without firmware changes.

At 0.27V core voltage, the BM1370 operates at the lower boundary of what current silicon processes can sustain reliably. This makes it particularly sensitive to power supply quality — any voltage noise, droop, or transient that would be inconsequential on a BM1398 running at 0.31V can cause hash errors or instability on the BM1370.

Specifications

Pin Configuration

The BM1370 BGA package follows the BM13xx family conventions with refinements for ultra-low-voltage operation. The ball map is not pin-compatible with the BM1368 — do not attempt to substitute one for the other.

Power Pins

• VDD — Core power supply (0.27V nominal). At this voltage, the current draw per chip is the highest in the BM13xx family despite the lower voltage, because the chip contains more active cores. Domain buck converters must maintain ±2% regulation under dynamic load — tighter than any previous Bitmain ASIC requirement.
• VDDIO — I/O power supply (1.8V). Used for communication interface and PLL analog blocks.
• VSS — Ground. The BM1370 has the most ground balls of any chip in the family to minimize package inductance, which is critical at 0.27V where even milliohms of parasitic resistance cause meaningful IR drop.

Communication Pins

• CI — Clock Input from upstream chip or controller.
• CO — Clock Output to downstream chip.
• RI — Receive Input (serial data from upstream).
• RO — Receive Output (serial data to downstream).
• BO — Break Out fault signal. The BM1370 adds additional fault detection logic that can distinguish between core failures and power delivery faults, reported through an extended status register.

PLL Pins

• XCLK — External clock reference (25 MHz typical). The BM1370's PLL has been redesigned with lower phase noise and faster lock time compared to the BM1368. It also supports fractional-N synthesis for fine-grained frequency tuning.

// PLL frequency register configuration for BM1370
// Note: BM1370 uses postdiv_minus_1 = true (unlike BM1398)
#define BM1370_PLL_FREQ_450M  0x00B0246401
#define BM1370_PLL_FREQ_500M  0x00B0286401
#define BM1370_PLL_FREQ_550M  0x00B02C6401
#define BM1370_PLL_FREQ_600M  0x00B0306401

Common Failure Modes

1. Voltage Margin Failures

The BM1370's 0.27V operating point leaves minimal noise margin. Failures that would be asymptomatic on older chips become critical.

Diagnosis:

• Measure VDD with a high-bandwidth oscilloscope (>100 MHz). Look for high-frequency switching noise, load transients, and droop during hash bursts.
• If the domain voltage shows more than 10mV of ripple, the output capacitors on the buck converter may be degraded. ESR increases over time, especially in high-temperature environments.
• Check for cold solder joints on the power plane vias — these add resistance to the supply path.

Root causes: Degraded output capacitors, PCB via cracking from thermal cycling, marginal buck converter components, or power supply ripple conducted from the 12V bus.

2. Dead Chip (Chain Break)

The chip does not respond to enumeration, breaking communication to all downstream chips.

Diagnosis:

• Standard chain-break diagnostic: probe CI/RI at the suspect chip to confirm signals arrive, then check CO/RO for output. No output with valid input confirms a dead chip.
• Measure VDD. A dead short on the die pulls the entire domain voltage down — check if the domain regulator is in current-limit or hiccup mode.
• If the chip is physically damaged (cracked die, detached solder balls), it may short VDD to VSS, affecting all chips in the domain.

3. Intermittent Hash Errors at Temperature

The chip works at room temperature but generates excessive HW errors as the board warms up to operating temperature (65–85°C at the chip surface).

Diagnosis:

• This typically indicates a marginal solder joint. As the board heats up, differential thermal expansion between the BGA balls and the PCB pads causes intermittent opens.
• Run the board while monitoring per-chip error rates and gradually increasing ambient temperature. If a specific chip's error rate spikes above 55°C, it likely needs rework.
• Inspect the chip under X-ray if available — look for head-in-pillow defects or cracked solder balls.

4. PLL Lock Failure

The chip enumerates but fails to lock its PLL to the target frequency. The chip may oscillate between locked and unlocked states, causing bursts of valid nonces followed by errors.

Diagnosis:

• Read the PLL status register. A chip that repeatedly loses lock may have a defective analog PLL circuit or insufficient VDDIO decoupling.
• Check the XCLK reference signal quality at the chip. Reflections or impedance mismatches on the clock distribution trace can prevent reliable lock.
• If multiple chips in the same area lose PLL lock, suspect a board-level VDDIO issue rather than individual chip faults.

Replacement Procedure

For detailed BGA rework techniques, see the BGA Rework Guide.

Found In These Miners

Compare With

• BM1368 — Previous generation 5nm chip for S21/T21. Slightly higher voltage (0.30V) and lower efficiency (~17.5 J/TH).
• BM1366 — Earlier 5nm chip for S19 XP. ~21.5 J/TH.
• BM1362 — 7nm chip for S19j Pro. Different process node entirely.
• BM1398 — Original S19-era 7nm chip. ~30 J/TH — nearly 2x less efficient.

Further Reading

• ASIC Chip Architecture
• Voltage Domains & Regulators
• Clock Distribution & PLL
• Cooling & Thermal Management
• ASIC Chip Comparison